FIG. 1 shows an example memory card system 100 of the prior art, including a memory card 102 and a host 104. The host 104 may be a portable electronic device such as a mobile phone, a MP3 player, or a PMP (portable media player). The memory card 102 may be a flash memory card as one example. The host 104 includes a host controller 106 and a host connection unit 108. The card 102 includes a card connection unit 110, a card controller 112, and a memory unit 114.
For writing data from the host 104 to the memory card 102, the host 104 sends a write command (WR_CMD), a clock signal CLK, and data to be written to the memory card 102 through the host connection unit 108. The memory card 102 receives the write command, the clock signal CLK, and the data through the card connection unit 110.
The card connection unit 110 receives the data from the host 104 in synchronism with the clock signal CLK from the host. The card controller 112 responds to the received write command by writing the received data into the memory unit 114 in synchronism with an internal clock signal generated by a clock signal generator within the card controller 112.
For reading of data from the memory card 102 by the host 104, the host 104 sends a read command (RD_CMD) and the clock signal CLK to the memory card 102 through the host connection unit 108. The memory card 102 receives the read command and the clock signal CLK through the card connection unit 110.
In the conventional memory card system 100, the host 104 generates and sends the clock signal CLK to be used by the memory card 110 for the write and read operations. Referring to the memory card system 100 in FIG. 2, the host 104 includes a host clock generator 116 for generating such a clock signal CLK.
Further referring to FIG. 2, the host 104 includes a host I/O (input/output) circuit 118 having a plurality of data flip flops HF1, HF2, . . . , and HFn that are clocked with the clock signal CLK from the host clock generator 116. The memory card 102 includes a card I/O (input/output) circuit 120 having a plurality of data flip flops CF1, CF2, . . . , and CFn that are also clocked with the clock signal CLK from the host clock generator 116. A card internal circuit 122 illustrated in FIG. 2 includes the card controller 112 and the memory unit 114 of FIG. 1.
FIG. 3 shows a flowchart of steps when the host 104 reads data from the memory card 102. FIG. 4 shows a timing diagram of signals when the host 104 reads data from the memory card 102.
Referring to FIGS. 2 and 3, the host generates and sends the read command (RD_CMD) and the clock signal CLK to the memory card 102 through the host connection unit 108 (step S1132 of FIG. 3). The memory card 102 upon receiving the read command through the card connection unit 110 reads data from the memory unit 114 in synchronism with an internal clock signal generated within the card controller 112 (step S134 of FIG. 3).
The memory card 102 then transfers the read data back to the host 104 in synchronism with the clock signal CLK from the host 104 (step S1136 of FIG. 3). In that case, the flip flops CF1, CF2, . . . , and CFn of the card I/O circuit 120 are clocked with the clock signal CLK from the host 104 for latching out such read data from the memory unit 114.
The host 104 receives and transfers such read data to the host controller 106 in synchronism to the clock signal CLK generated by the clock signal generator 116 at the host 104 (step S138 of FIG. 3). In that case, the flip flops HF1, HF2, . . . , and HFn of the host I/O circuit 118 are clocked with the clock signal CLK generated by the clock signal generator 116 at the host 104.
FIG. 4 shows a timing diagram of signals for the read operation within the memory card system 100 of FIG. 2. FIG. 4 shows the original CLK signal S10 generated by the clock signal generator 116 at the host 104. FIG. 4 also shows the transmitted CLK signal S20 received at the memory card 102 which is time delayed by time period t1 from the original CLK signal S10.
Additionally referring to FIG. 4, data S30 is output from the card I/O circuit 120 at a time delay t2 from the transmitted CLK signal S20 received at the memory card 102. The time delay t2 is a portion of the time period required for the memory controller 112 to retrieve the read data S30 from the memory 114 with respect to the received CLK signal S20 after receiving the read command. The total time delay t I+t2=t3 is also termed an output delay.
For example, the first data D0 begins to be generated at time point tp1 by the card controller 112 after the read command has been received by the controller 112 at a prior time. For example, the read command may have been received at the C0 transition of the CLK signal S20 received at the card 102. Thus, the data S30 is invalid (shown as shaded in FIG. 4) before the time point tp1.
Further referring to FIG. 4, data S40 is received at the host 104 with a bus delay t4 which is the time period required for transferring the data from the card 102 to the host 104. Once the data S40 arrives at the host connection unit 108, the host I/O circuit 118 has a maximum allowable setup time period t5 for transferring such data S40 to the host controller 106. The maximum allowable setup time period t5 is from the end of the time period t4 until the subsequent transition of the original clock signal CLK at the host 104 when the flip flops HF1, HF2, . . . , and HFn of the host I/O circuit 118 are controlled to latch the received data S40.
Thus, in the prior art, the maximum allowable setup time period t5 is limited by the output delay t3 and the bus delay t4. However, such allowable setup time period t5 may limit high frequency operation of the memory card system 100. Thus, a mechanism is desired for increasing the allowable setup time period t5 for faster speed performance of the memory card system.